In general, an application specific integrated circuit (ASIC) design process includes two main design phases, such as an RTL (register transfer level) design phase and a physical design phase. An RTL design phase is performed by converting a user specification of integrated circuit function into an RTL description, which specifies how each portion of the integrated circuit operates on each clock cycle. In the physical design phase, an integrated circuit design is generated using a corresponding RTL file and a library of standard component cells such as basic logic gates (AND gate, OR gates, NAND gates, NOR gates, etc.) and macro cells such as adders, multiplexers, flip-flops, memory, etc. More specifically, a physical design phase includes various phases such as logic synthesis, placement, clock-tree synthesis, and routing. The use of shift registers is very common in ASIC design. In general, a shift register comprises a cascade of flip-flops in which an output of each flip-flop is connected to a “data” input of a next flip-flop in the shift register chain. Shift registers are used for various purposes such as scan testing for Design For Testing (DFT) applications, and a myriad of other functional purposes as is known by those of ordinary skill in the art. However, a shift register can consume a large amount of chip area, waste a significant amount of power through leakage current, and requires complex routing that results in wiring congestion due to the large amount of pins of the individual flip-flop cells that must be connected to implement the shift register.